Intro
I’m a final year undergraduate at the University of Washington, where I study computer science. I work in the PLSE group at UW.
Next year, I’ll start my PhD in Electrical Engineering at Stanford University! I’m excited to move to sunny California, but secretly I will miss the cold breeze of Seattle in the winter.
News
Mar. 2024 – Accepted PhD At Stanford!
Mar. 2024 – Our workshop paper on using egraphs for EDA tasks was accepted to Latte!
Dec. 2023 – 3LA was accepted to TODAES 2023!
Dec. 2023 – Lakeroad was accepted to ASPLOS 2024!
Research
Generally, I’m interested in compilers and programming languages, especially with applications in hardware and computer architecture. Currently, I work on Lakeroad, a tool for FPGA synthesis, via sketch-guided synthesis. In the past, I’ve worked on the 3LA project, a development methodology for end-to-end testing of specialized hardware. I’ve additionally contributed to Glenside, a language for tensor program rewriting, and a formal specification mutation generator named Gambit.
I’ve been very lucky to work with a great group of colleagues and mentors in industry and academia. At UW, I’m thankful to have be been advised by Zachary Tatlock and Gus Smith on all the projects I’ve worked on.
At Certora, I was advised by Chandrakana Nandi, who generously took on a very inexperienced sophomore and molded him into a (potentially) great researcher!
Publications
There and Back Again: A Netlist’s Tale with Much Egraphin’
(LATTE 2024)
Gus Henry Smith, Zachary D. Sisco, Thanawat Techaumnuawit, Jingtao Xia, Vishal Canumalla, Andrew Cheung, Zachary Tatlock,
Chandrakana Nandi, Jonathan Balkind
FPGA Technology Mapping Using Sketch-Guided Program Synthesis
(ASPLOS 2024)
Gus Henry Smith, Benjamin Kushigian, Vishal Canumalla, Andrew Cheung, Steven Lyubomirsky, Sorawee Porncharoenwase, René Just, Zachary Tatlock
Application-Level Validation of Accelerator Designs Using a Formal Software/Hardware Interface.
(TODAES 2023)
Bo-Yuan Huang, Steven Lyubomirsky, Yi Li, Mike He, Thierry Tambe, Gus Henry Smith, Akash Gaonkar, Vishal Canumalla, Andrew Cheung, Gu-Yeon Wei, Aarti Gupta, Zachary Tatlock, Sharad Malik.
Generate Compilers from Hardware Models!
(PLARCH 2023)
Gus Henry Smith, Ben Kushigian, Vishal Canumalla, Andrew Cheung, René Just, Zachary Tatlock
Talks and Posters
Application of Sketch-Guided Synthesis to Runtime Reconfigurable FPGA Primitives
(ICFP SRC 2023)
Vishal Canumalla
3rd Place in Undergraduate Category
About
I was born in Dallas Texas, but home to me will always be Washington. I’ve lived here since I was 6!
I used to want to study chemistry in high school, before settling on doing chemistry and computer science. Now I only study computer science. I wonder if it will come full circle one day…
My hobbies are mostly non-technical. I especially enjoy fantasy in any medium: games, books, movies, anything really. I also am an avid wildlife photographer. I find animals give far less criticism on their portraits than my human friends do.
I enjoy snowboarding (decent), tennis (mediocre), basketball (horrendous), and running (improving)!
I have an older brother Ani, who is a Ph.D. student at UCSD CSE. He’s much smarter than me, but I keep up by learning from his example.
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